The invention is in the field of field effect transistor (FET) devices, and relates specifically to lateral junction field effect transistor (JFET) devices.
Such transistors are well-known in the art, and one such device is shown in Japanese Kokai No. 55-153378. This device includes a semiconductor substrate of a first conductivity type (p-type), a first semiconductor layer of a second conductivity type (n-type), and source, gate and drain contact regions located at the surface of the first semiconductor layer, with the gate region being of the first conductivity type and located between the source and drain contact regions, which are of the second conductivity type. This device is electrically isolated from adjacent portions of the first semiconductor layer by isolation zones of the first conductivity type. Finally, this device includes a buried semiconductor layer of the second conductivity type which has a doping level less than that of the first semiconductor layer, the buried layer being located between the first layer and the substrate so as to form a p-n junction with the substrate and extend beneath the source, gate and drain contact regions of the device. This lightly-doped buried semiconductor layer has a graduated doping concentration and is included for the purpose of reducing the back gate capacitance of the device.
For high-voltage applications, it has been found that the breakdown characteristics of semiconductor devices can be improved by using the REduced SURface Field (RESURF) technique, as described in "High Voltage Thin Layer Devices (RESURF Devices)", "International Electronic Devices Meeting Technical Digest", December, 1979, pages 238-240, by Appels et al. Application of the RESURF technique to bipolar transistors, junction field effect transistors and insulated-gate field effect transistors is shown in U.S. Pat. No. 4,292,642 to Appels et al and U.S. Pat. No. 4,300,150 to Colak. In general terms, the RESURF technique used in these references serves to improve high-voltage device breakdown characteristics by reducing surface field levels through the use of modified thickness and doping characteristics in the semiconductor layers of the device.
Heretofore, junction field effect transistors have suffered from several drawbacks which have limited their utility in high-voltage applications. Specifically, prior-art high-voltage junction field effect transistors using the RESURF technique are not capable of operating effectively in the source-follower mode, due to the high gate potentials and resultant punch-through breakdown associated with this mode of operation. Furthermore, prior-art JFET devices are not normally operated with a forward gate bias in the "on" state because this would be of no advantage in conventional devices, where the injected carriers would simply diffuse into the substrate. However, the use of forward gate bias in the "on" state would be a potentially valuable technique for enhancing device conductivity in a device configuration in which such forward gate bias could effectively modulate channel resistivity.
Thus, known junction field effect transistor devices are not capable of operating in the source-follower mode and also providing relatively high breakdown voltage levels and a relatively low on-resistance.